[Pigasus] Pigasus Developer's Meeting: 5/4 at 1PM

[Justine Sherry]

Dear All,

We are excited to host Nirav Atre for the 5/4 edition of the Pigasus
Developer's Meeting, where he will be presenting on the BBQ programmable
queue.

Please join us at 1PM ET on 5/4
https://cmu.zoom.us/j/93115144458?pwd=ZUVZY2VDN1ZtUlIwRDNiZXFPWm1oUT09
<https://www.google.com/url?q=https://cmu.zoom.us/j/93115144458?pwd%3DZUVZY2VDN1ZtUlIwRDNiZXFPWm1oUT09&sa=D&source=calendar&usg=AOvVaw2tGfasb3CZqpxllBMbXbX8>

ABSTRACT:
The need for fairness, strong isolation, and fined-grained control over
network traffic in multi-tenant cloud settings has engendered a rich
literature on packet scheduling in switches and programmable hardware.
Recent advancements in hardware scheduling primitives (PIFO, PIEO, etc.)
have enabled switch manufacturers to deploy run-time programmable packet
schedulers at high throughput, considerably expanding the suite of
scheduling policies that can be realized on modern switches. However,
existing designs suffer serious scalability shortcomings:  the hardware
complexity of these designs makes it infeasible to support a large number
of distinct flows while achieving line-rate (100Gbps) performance.

In this work, we ask: is it possible to achieve priority packet scheduling
at line-rate while supporting a large number of flows? Our key insight is
to leverage a scheduling primitive used previously in software -- called
Hierarchical Find First Set -- and port this to a highly pipeline-parallel
hardware design. We present the architecture and implementation of
Bitmapped Bucket Queue (\system), a hardware-based integer priority queue
that supports a wide range of scheduling policies (via a PIFO-like
abstraction), while achieving line-rate performance with minimum-sized
packets. BBQ, for the first time, supports hundreds of thousands of
concurrent flows while guaranteeing line rate, not only on ASIC, but also
on FPGAs. We implement BBQ on a commodity FPGA where it is capable of
supporting 100K+ flows and 32K+ priorities at 250MHz, 2X the number of
flows and 8X the packet rate of similar hardware priority queue designs. On
ASIC, we can synthesize 100k entries at 1GHz using a 15nm process.

Please forward to any friends or colleagues who might be interested!!
--
Justine Sherry (she/her)
Assistant Professor, Computer Science
Carnegie Mellon University
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